I am half way through my exams at the moment. I have 2 more left and one of those is tomorrow. So far i dont know how i'm doing, Control2 was difficult and VLSI was grand. I'm dreading tomorrows exam (telecommunications). I really hate having to learn about all this vector encoding crap and how it applies to the OSI network model. I have zero interest in any job involving telecommunications, if i did, i'd have done a different course or would have stuck with Computer Engineering instead of switching to Electronic.

My ranting will get me nowhere though. Like it or not i have to sit this exam tomorrow. I'm not sure what the structure will be like, but if it resembles last year (MCQs followed by long questions) i'll be okay. It's not on until 4pm anyway so i can do some last minute cramming. Then on Saturday i have my final exam which is ASICS2. This should be okay. I'm the only person in the class so i feel this extra responsibility to do well. The exam paper is really interesting though, like there's a design question based on a HSPICE file, and you have to determine all the steady state currents and voltages based on this file.

While all my exams are finished on Saturday, i won't have anytime for celebrating as i still have to finish my Sigma Delta Modulator design. I have the basic hardware laid out. I'm concerned about the latched comparator part. Basically i wasn't sure how to design a latched comparator when i have a PMOS differential pair in my comparator, so i just put a latch on the output...as in 4 NAND gates. It's really inefficient so if there's anyone reading this and knows how to design a latched comparator, please send it to me.

I need to finish this project by Monday. Then i'll be free to enjoy the Breeders which i'm going to on Monday night. I have 4 days of hardship ahead.