20% finished
Yesterday i had my first exam, which i think i mentionned was for Signals and Systems 2. It didn't go as badly as i expected. We had to answer 4 out of 6 questions and i got the better part of 5 questions out. I dont want to overanalyse and freak myself out so i'm just going to forget about it until the results are released.
My next exam is in 6 days time and it's ASICs (Application Specific Integrated Circuits). This is mostly Verilog coding with a bit on CMOS devices thrown in at the end. Luckily for me Active Circuit Design 4 is totally based on CMOS devices to that part shouldn't be a problem. Verilog isn't too bad. 40% of this module was going for a verilog filter desgin project we had to do. Currently i'm at 30% because i still have to hand in my report for this.
This semester has definitelty been the toughtest. I know that as college goes on it's meant to get exponentially more difficult. When i told my FYP supervisors how crazy this semester has been they just laugh and say "wait till next you come back in Janurary, things really get tough then", which is zero comfort! It just seems that there's so many projects and assignments that it leaves little time for actual study.
My mother is a Lecturer in Economics in a different college. The 4th years she teaches don't take an end of semester exam because the course is based on continuous assesment. She divides this up into a 40% midterm and the other 60% goes for a research essay and a 15 minute presentation on the essay. For our telecommunications module this semester, we had to write a research essay and do a presentation on it and it was only worth 10%!!! My sister is doing science in UCD and her whole class had to go on a field trip for a weekend. It was for some kind of environmetal biology study. Apparently they were all worked to the bone for the weekend and when they got back they found out it was only worth 2% of the module.....Its actually kinda funny when you think about it, although maybe thats just because i listened to her rant about this. So in summary, if there are any leaving cert students reading this, go for economics in WIT and ignore engineering in UL or science in UCD!
My next exam is in 6 days time and it's ASICs (Application Specific Integrated Circuits). This is mostly Verilog coding with a bit on CMOS devices thrown in at the end. Luckily for me Active Circuit Design 4 is totally based on CMOS devices to that part shouldn't be a problem. Verilog isn't too bad. 40% of this module was going for a verilog filter desgin project we had to do. Currently i'm at 30% because i still have to hand in my report for this.
This semester has definitelty been the toughtest. I know that as college goes on it's meant to get exponentially more difficult. When i told my FYP supervisors how crazy this semester has been they just laugh and say "wait till next you come back in Janurary, things really get tough then", which is zero comfort! It just seems that there's so many projects and assignments that it leaves little time for actual study.
My mother is a Lecturer in Economics in a different college. The 4th years she teaches don't take an end of semester exam because the course is based on continuous assesment. She divides this up into a 40% midterm and the other 60% goes for a research essay and a 15 minute presentation on the essay. For our telecommunications module this semester, we had to write a research essay and do a presentation on it and it was only worth 10%!!! My sister is doing science in UCD and her whole class had to go on a field trip for a weekend. It was for some kind of environmetal biology study. Apparently they were all worked to the bone for the weekend and when they got back they found out it was only worth 2% of the module.....Its actually kinda funny when you think about it, although maybe thats just because i listened to her rant about this. So in summary, if there are any leaving cert students reading this, go for economics in WIT and ignore engineering in UL or science in UCD!
